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83 lines
2.9 KiB
83 lines
2.9 KiB
%! Detailed register description file for PCICFG.EXE by Ralf Brown
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%!
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%! Filename 80867111.PCI = Vendor 8086h, Device 7111h
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%! Intel 82731AB PIIX4 Ultra DMA/33 IDE Controller
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%! Last Edit 31 Dec 1997 by Andy Sawyer
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%!
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%! Reference : Intel document 29056201.PDF
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%! "82371AB PCI-TO-ISA/IDE XCELERATOR (PIIX4)"
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%!
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%! See also : 80867110.PCI,80867112.PCI,80867113.PCI
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%!
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%! Note, the entry listed below as "Fast Timing" is rather confusingly
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%! described by intel as "DMA Timing Enable Only", although it doesn't
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%! actually affect the timing for DMA operations...
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%!
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!begin
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Intel 82371AB PIIX4 IDE Controller registers in detail: [by Andy Sawyer]
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IDE Timing Modes
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Primary Channel %[40:15]ed
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Slave Timing Register %[40:14]ed
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IORDY Sample Point %[40:13-12]{5432} clocks after DIOx#
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Recovery Time after IORDY %[40:9-8]{4321} clock(s)
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Drive 0:
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Fast Timing %[40:3](FastTiming)
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Prefetch and Posting %[40:2]ed
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IORDY Sample Point Drive Select %[40:1]ed
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Fast Timing Bank Drive Select %[40:0]ed
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Drive 1:
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Fast timing %[40:7](FastTiming)
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Prefetch and Posting %[40:6]ed
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IORDY Sample Point Drive Select %[40:5]ed
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Fast Timing Bank Drive Select %[40:4]ed
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Secondary Channel %[42:15]ed
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Slave Timing Register %[42:14]ed
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IORDY Sample Point %[42:13-12]{5432} clocks after DIOx#
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Recovery Time after IORDY %[42:9-8]{4321} clock(s)
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Drive 0:
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Fast timing %[42:3](FastTiming)
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Prefetch and Posting %[42:2]ed
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IORDY Sample Point Drive Select %[42:1]ed
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Fast Timing Bank Drive Select %[42:0]ed
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Drive 1:
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Fast timing %[42:7](FastTiming)
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Prefetch and Posting %[42:6]ed
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IORDY Sample Point Drive Select %[42:5]ed
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Fast Timing Bank Drive Select %[42:4]ed
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Slave IDE Timing Register
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Primary Drive 1:
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IORDY Sample Point %[44:3-2]{5432} clocks after DIOx#
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Recovery Time %[44:1-0]{4321} clock(s)
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Secondary Drive 1:
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IORDY Sample Point %[44:7-6]{5432} clocks after DIOx#
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Recovery Time %[44:5-4]{4321} clock(s)
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Ultra DMA/33 Control Register
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Primary Drive 0 UDMA %[48:0]ed
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Primary Drive 1 UDMA %[48:1]ed
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Secondary Drive 0 UDMA %[48:2]ed
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Secondary Drive 1 UDMA %[48:3]ed
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Ultra DMA/33 Timing Register
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Primary Drive 0 Cycle Time %[4A:1-0](UDMATiming)
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Primary Drive 1 Cycle Time %[4A:5-4](UDMATiming)
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Secondary Drive 0 Cycle Time %[4A:9-8](UDMATiming)
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Secondary Drive 1 Cycle Time %[4A:13-12](UDMATiming)
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!end
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!enum FastTiming
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DMA & PIO Modes
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DMA mode only
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!end
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!enum UDMATiming
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4/6
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3/5
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2/4
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Reserved
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!end
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%! end of file
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