%! Detailed register description file for PCICFG.EXE by Ralf Brown
%!
%! Filename 80861235.PCI = Vendor 8086h, Device 1235h -- Intel 82437MX
%! Last Edit 1/17/97 by Ralf Brown
%!

Everything preceding a line beginning with the six characters "!begin" is
a comment and will be ignored (with the proviso that the total file size
not exceed 64K).  Everything from the !begin line to a line starting with
the four characters "!end" forms part of the device description, in a
format similar to that used for printf().

[See file BLANK.PCI for description of formatting specification and how
to create your own device descriptions.]


!begin
82437MX System Controller registers in detail:
 PCI Control:     PeerConcurr=%[50:3]y PCIburst=%[50:2]n PCIstream=%[50:1]n BusConcurr=%[50:0]n CPUinact=%[50:7-5+1]d
 Cache Control:   cache size    %[52:7-6]|0K;256K;512K;reserved|
		  L2 RAM type   %[52:5-4]|p.burst;async;reserved;two banks p.burst|
		  Force L2 miss  %[52:1]y\tL1 cache %[52:0]Ed\tNA# %[52:3]Ed
 DRAM control:    DRAMs are %[57:4]|NOT;| self-refreshing
		  refresh   = %[57:2-0]|15.6;32.2;62.4;125;250;reserved| microseconds
		  DRAM hole = %[57:7-6]|none;512K-640K;15M-16M;reserved|
		  EDO Detect mode is %[57:3]ed
 Memory Top:      %[63]3dM
 DRAM Boundaries: %[60]3dM %[61]3dM %[62]3dM %[63]3dM
 DRAM Row Type:   %[68:0]|FPM;EDO|  %[68:1]|FPM;EDO|  %[68:2]|FPM;EDO|  %[68:3]|FPM;EDO|
 DRAM timing:     read burst   = %[58:6-5]|x444/x444;x333/x444;x222/x333;x322/x333|
		  write burst  = %[58:4-3]|x444;x333;x222;reserved|
		  RAS-to-CAS   = %[58:2]|3;2| clocks
		  DRAM leadoff = %[58:1-0]|8/6/3;7/5/3;8/6/4;7/5/4| (read/write/precharge)
		  MA[11:2] buffer strength is %[58:7]|8;12|mA
 Programmable Attribute Map
	C000-C3FF: %[5A:2]{-C}%[5A:1]{-W}%[5A:0]{-R}\tD000-D3FF: %[5C:2]{-C}%[5C:1]{-W}%[5C:0]{-R}\tE000-E3FF: %[5E:2]{-C}%[5E:1]{-W}%[5E:0]{-R}%
	F000-FFFF: %[59:6]{-C}%[59:5]{-W}%[59:4]{-R}
	C400-C7FF: %[5A:6]{-C}%[5A:5]{-W}%[5A:4]{-R}\tD400-D7FF: %[5C:6]{-C}%[5C:5]{-W}%[5C:4]{-R}\tE400-E7FF: %[5E:6]{-C}%[5E:5]{-W}%[5E:4]{-R}
	C800-CBFF: %[5B:2]{-C}%[5B:1]{-W}%[5B:0]{-R}\tD800-DBFF: %[5D:2]{-C}%[5D:1]{-W}%[5D:0]{-R}\tE800-EBFF: %[5F:2]{-C}%[5F:1]{-W}%[5F:0]{-R}
	CC00-CFFF: %[5B:6]{-C}%[5B:5]{-W}%[5B:4]{-R}\tDC00-DFFF: %[5D:6]{-C}%[5D:5]{-W}%[5D:4]{-R}\tEC00-EFFF: %[5F:6]{-C}%[5F:5]{-W}%[5F:4]{-R}
 SMRAM control:    SMM Space at segment %[72:2-0+8]1x000 is %[72:6]/open/ %[72:5]/closed/ %[72:4]/locked/
!end

; everything between the above !end line and a following !enum line (not
; yet implemented) is also a comment

!enum ToBeImplemented



%! end of file