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122 lines
4.5 KiB
122 lines
4.5 KiB
3 years ago
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%! Detailed register description file for PCICFG.EXE by Ralf Brown
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%!
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%! Filename 80867100.PCI = Vendor 8086h, Device 7100h
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%! Intel 82439TX System Controller
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%! Created 31 Dec 97 by Andy Sawyer
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%! Last edit 10jan99 by Ralf Brown
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%!
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%! Reference : Intel document 29055901.PDF
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%! "Intel 430TX PCISET : 82439TX System Controller (MTXC)"
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%!
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!begin
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82439TX System Controller registers in detail: [by Andy Sawyer]
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Extended CPU-to-PIIX4 PHLDA# Signalling: %[4F:7]ed
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PCI Concurrency Enable: %[50:3]ed
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ACPI Control Register: %[79:6]ed
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Suspend Refresh Type : %[79:5]|CBR Refresh;Self Refresh|
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Normal Refresh Enable: %[79:4]y
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Internal Clock Control: %[79:2]ed
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Cache Control:
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Seconday Cache Size: %[52:7-6]|Not Populated;256K;512K;Reserved|
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L2 SRAM Type: %[52:5-4]|Pipelined Burst SRAM;Reserved;Reserved;Two banks of pipelined burst SRAM|
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NA Disable: NA is %[52:3]Ed
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Secondary Cache Force Miss: %[52:1]y
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First Level Cache Enable: %[52:0]ed
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DRAM Cache L2 present: %[53:5]y
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DRAM Cache L2 refresh timer: %[53:4-0]d
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SDRAM Control:
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Special SDRAM mode select: %[54:8-6](SDMS)
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RAS# to CAS# Override: %[54:5]ed
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CAS# Latency: %[54:4]{23}
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RAS# Timing: %[54:3]|3/5/8;3/4/7|
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64-MBit Technology Enable: %[54:1]y
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DRAM Control:
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Refresh RAS# Assertion: %[56:6]{45} Clocks
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Fast EDO Lead Off: %[56:5]ed
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Speculative Lead Off: %[56:4]Ed
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Memory Address Drive Strength: %[56:2]|10;16|ma %[56:1]|10;16|ma
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Memory Hole: %[57:7-6]|none;512K-640K;15M-16M;14M-16M|
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Enhanced Paging: %[57:4]ed
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Detect Mode: %[57:3]ed
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Refresh Rate: %[57:2-0]|disabled;15.6;31.2;64.4;125;256;Reserved|
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DRAM Timing:
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Read Burst Timing: %[58:6-5]|x444/x444;x333/x444;x222/x333;Reserved|
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Write Burst Timing: %[58:4-3]|x444;x333;x222;Reserved|
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Leadoff Timing: Read %[58:0]|11;10| Write %[58:0]{76}
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RAS# Precharge %[58:1]{34}
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RAS-to-CAS Delay %[58:0]{43}
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DRAM Boundaries: %[60]3dM %[61]3dM %[62]3dM
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%[63]3dM %[64]3dM %[65]3dM
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DRAM Row Type:
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Host Frequency: %[67:7]|60;66|MHz
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DRAM Row Type: Row 0: %[68:4]b%[68:0]b Row 3: %[68:7]b%[68:3]b
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00=SPM 01=EDO Row 1: %[68:5]b%[68:1]b Row 4: %[67:4]b%[67:0]b
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10=SDRAM Row 2: %[68:6]b%[68:2]b Row 5: %[67:5]b%[67:1]b
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11=Reserved
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Memory Address Select Enable: %[67:2]d
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%! Note: Intel don't document leadoff timing as the above in as many words,
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%! but the answers are still the same :-)
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Programmable Attribute Map
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0F000-0FFFF: %[59:6]{-C}%[59:5]{-W}%[59:4]{-R}\t0C000-0C3FF: %[5A:2]{-C}%[5A:1]{-W}%[5A:0]{-R}
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0C400-0C7FF: %[5A:6]{-C}%[5A:5]{-W}%[5A:4]{-R}\t0C800-0CBFF: %[5B:2]{-C}%[5B:1]{-W}%[5B:0]{-R}
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0CC00-0CFFF: %[5B:6]{-C}%[5B:5]{-W}%[5B:4]{-R}\t0D000-0D3FF: %[5C:2]{-C}%[5C:1]{-W}%[5C:0]{-R}
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0D400-0D7FF: %[5C:6]{-C}%[5C:5]{-W}%[5C:4]{-R}\t0D800-0DBFF: %[5D:2]{-C}%[5D:1]{-W}%[5D:0]{-R}
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0DC00-0DFFF: %[5D:6]{-C}%[5D:5]{-W}%[5D:4]{-R}\t0E000-0E3FF: %[5E:2]{-C}%[5E:1]{-W}%[5E:0]{-R}
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0E400-0E7FF: %[5E:6]{-C}%[5E:5]{-W}%[5E:4]{-R}\t0E800-0EBFF: %[5F:2]{-C}%[5F:1]{-W}%[5F:0]{-R}
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0EC00-0EFFF: %[5F:6]{-C}%[5F:5]{-W}%[5F:4]{-R}
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Multi-Transaction Timer: %[70:7-2]d
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System Management RAM Control:
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SMM Space Open: %[73:6]y
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SMM Space Closed: %[73:5]y
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SMM Space Locked: %[73:4]y
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Global SMRAM Enble: %[73:3]y
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Compatible SMM Space base Seg: %[73:2-0](C_BASE_SEG)
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High SMRAM Enable: %[71:7]e
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Extended SMRAM Error: %[71:6]y
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SMRAM Cache Strategy: %[71:5]|WriteBack;WriteThru|
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SMRAM L1 Cache Enable: %[71:4]e
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SMRAM L2 Cache Enable: %[71:3]e
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TSEG Size: %[72:2-1](TSEG_SZ)
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TSEG Enable: %[72:0]y
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!end
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!enum SDMS
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Normal SDRAM mode
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NOP Command Enable
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All Banks Precharge Command Enable
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Mode Register Command Enable
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CBR Cycle Enable
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Reserved
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Reserved
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Reserved
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Reserved
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!end
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!enum TSEG_SZ
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(TOM-128k) to TOM
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(TOM-256k) to TOM
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(TOM-512k) to TOM
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(TOM-1MB) to TOM
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!end
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!enum C_BASE_SEG
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Reserved
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Reserved
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A0000-BFFFFh
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Reserved
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Reserved
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Reserved
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Reserved
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Reserved
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!end
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%! end of file
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