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292 lines
7.5 KiB
292 lines
7.5 KiB
3 years ago
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SYSTEM-MANAGEMENT MODE Release 61 Last change 16jul00
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Copyright (c) 1997,1998,1999,2000 Ralf Brown
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---------------------------------------------
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SMM Am486
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Format of Am486 SMM State-Save Map:
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Offset Size Description (Table S0001)
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FE00h reserved
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FEE4h DWORD DR3
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FEE8h DWORD DR2
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FEECh DWORD DR1
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FEF0h DWORD DR0
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FEF4h DWORD CR2
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FEF8h DWORD SMM state dump base address
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fEFCh DWORD SMM revision ID (see #S0004)
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FF00h WORD I/O restart
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(set to 00FFh to re-execute trapped I/O)
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FF02h WORD halt auto restart
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(bit 0 set on entry if SMI during HLT)
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(set to 00FFh to restart from HLT)
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FF04h DWORD I/O trap word (see #S0002)
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FF08h DWORD reserved
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FF0Ch DWORD reserved
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FF10h DWORD previous EIP
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FF14h 5 DWORDs ???
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FF28h DWORD reserved
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FF2Ch DWORD reserved
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FF30h DWORD ES limit
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FF34h DWORD ES base
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FF38h DWORD ES attributes
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FF3Ch DWORD CS limit
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FF40h DWORD CS base
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FF44h DWORD CS attributes
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FF48h DWORD SS limit
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FF4Ch DWORD SS base
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FF50h DWORD SS attributes
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FF54h DWORD DS limit
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FF58h DWORD DS base
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FF5Ch DWORD DS attributes
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FF60h DWORD FS limit
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FF64h DWORD FS base
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FF68h DWORD FS attributes
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FF6Ch DWORD GS limit
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FF70h DWORD GS base
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FF74h DWORD GS attributes
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FF78h DWORD LDT limit
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FF7Ch DWORD LDT base
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FF80h DWORD LDT attribute
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FF84h DWORD GDT limit
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FF88h DWORD GDT base
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FF8Ch DWORD GDT attribute
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FF90h DWORD IDT limit
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FF94h DWORD IDT base
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FF98h DWORD IDT attribute
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FF9Ch DWORD TSS limit
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FFA0h DWORD TSS base
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FFA4h DWORD TSS attribute
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FFA8h WORD ES
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FFAAh WORD unused???
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FFACh WORD CS
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FFAEh WORD unused???
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FFB0h WORD SS
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FFB2h WORD unused???
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FFB4h WORD DS
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FFB6h WORD unused???
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FFB8h WORD FS
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FFBAh WORD unused???
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FFBCh WORD GS
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FFBEh WORD unused???
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FFC0h DWORD LDTR
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FFC4h DWORD TR
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FFC8h DWORD DR7
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FFCCh DWORD DR6
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FFD0h DWORD EAX
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FFD4h DWORD ECX
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FFD8h DWORD EDX
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FFDCh DWORD EBX
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FFE0h DWORD ESP
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FFE4h DWORD EBP
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FFE8h DWORD ESI
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FFECh DWORD EDI
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FFF0h DWORD EIP
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FFF4h DWORD EFLAGS
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FFF8h DWORD CR3
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FFFCh DWORD CR0
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SeeAlso: #S0003
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Bitfields for AMD Am486 I/O trap word:
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Bit(s) Description (Table S0002)
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31-16 I/O address
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15-2 reserved
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1 valid I/O instruction
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0 direction
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SeeAlso: #S0001
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---------------------------------------------
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SMM AMD-K5
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Format of AMD K5 SMM State-Save Area:
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Offset Size Description (Table S0003)
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FE00h reserved
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FEF8h DWORD SMM base address
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(may be set to any multiple of 32K; initially 00030000h)
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FEFCh DWORD SMM revision identifier (see #S0004)
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FF00h WORD I/O trap restart slot (see #S0007)
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FF02h WORD HLT restart slot (see #S0005)
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FF04h DWORD I/O restart EDI
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FF08h DWORD I/O restart ECX
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FF0Ch DWORD I/O restart ESI
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FF10h DWORD CR4
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FF14h DWORD CR2
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FF18h 3 DWORDs reserved
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FF24h DWORD ES limit
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FF28h DWORD ES base
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FF2Ch DWORD ES attributes
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FF30h DWORD CS limit
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FF34h DWORD CS base
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FF38h DWORD CS attributes
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FF3Ch DWORD SS limit
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FF40h DWORD SS base
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FF44h DWORD SS attributes
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FF48h DWORD DS limit
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FF4Ch DWORD DS base
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FF50h DWORD DS attributes
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FF54h DWORD FS limit
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FF58h DWORD FS base
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FF5Ch DWORD FS attributes
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FF60h DWORD GS limit
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FF64h DWORD GS base
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FF68h DWORD GS attributes
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FF6Ch DWORD LDT limit
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FF70h DWORD LDT base
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FF74h DWORD LDT attributes
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FF78h DWORD TSS limit
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FF7Ch DWORD TSS base
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FF80h DWORD TSS attributes
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FF84h DWORD GDT limit
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FF88h DWORD GDT base
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FF8Ch DWORD IDT limit
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FF90h DWORD IDT base
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FF94h 2 DWORDs reserved
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FF9Ch DWORD I/O trap EIP
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FFA0h DWORD reserved
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FFA4h DWORD I/O trap DWORD (see #S0006)
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FFA8h WORD ES
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FFAAh WORD unused???
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FFACh WORD CS
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FFAEh WORD unused???
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FFB0h WORD SS
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FFB2h WORD unused???
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FFB4h WORD DS
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FFB6h WORD unused???
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FFB8h WORD FS
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FFBAh WORD unused???
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FFBCh WORD GS
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FFBEh WORD unused???
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FFC0h DWORD LDTR
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FFC4h DWORD TR
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FFC8h DWORD DR7
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FFCCh DWORD DR6
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FFD0h DWORD EAX
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FFD4h DWORD ECX
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FFD8h DWORD EDX
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FFDCh DWORD EBX
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FFE0h DWORD ESP
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FFE4h DWORD EBP
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FFE8h DWORD ESI
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FFECh DWORD EDI
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FFF0h DWORD EIP
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FFF4h DWORD EFLAGS
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FFF8h DWORD CR3
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FFFCh DWORD CR0
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SeeAlso: #S0001
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Bitfields for AMD K5 SMM Revision Identifier:
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Bit(s) Description (Table S0004)
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31-18 reserved (0)
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17 SMM base address relocation available (always 1 [enabled] on K5)
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16 I/O trap restart supported (always 1 on K5)
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15-0 SMM revision level (currently 0000h)
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SeeAlso: #S0003
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Bitfields for AMD K5 Halt Restart Slot:
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Bit(s) Description (Table S0005)
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15-1 undefined
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0 (on SMM entry) entered SMM from Halt state
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(at RSM) return to Halt state instead of state in SMM state-save area
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SeeAlso: #S0003
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Bitfields for AMD K5 I/O Trap DWORD:
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Bit(s) Description (Table S0006)
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31-16 I/O port address
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15 I/O was string operation (INS,OUTS,etc.)
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14-2 reserved
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1 valid I/O instruction
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0 direction (0 = output, 1 = input)
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SeeAlso: #S0003,#S0007
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Bitfields for AMD K5 I/O Trap Restart Slot:
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Bit(s) Description (Table S0007)
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31-16 reserved
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15-0 I/O instruction restart on RSM
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0000h resume at next instruction following trapped I/O instruction
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(default on SMM entry)
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00FFh re-execute the trapped I/O instruction
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Note: before changing the restart value, check that the I/O instruction is
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actually valid (see #S0006)
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SeeAlso: #S0003,#S0006
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---------------------------------------------
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SMM Pentium
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Format of Pentium State Dump record:
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Offset Size Description (Table S0008)
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FE00h 248 BYTEs officially reserved, actually unused
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FEF8h DWORD state dump base address (must be multiple of 32K)
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FEFCh DWORD SMM revision identifier
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bits 15-0: SMM revision level
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bit 16: I/O trap extension is present (offset FF00h)
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bit 17: SMM base relocation supported (offset FEF8h)
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bits 31-18: reserved
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FF00h WORD I/O Trap restart
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(set to 00FFh to re-execute trapped I/O)
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FF02h WORD Halt auto-restart
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(bit 0 set on entry if SMI during HLT; if handler clears it,
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the CPU returns to the instruction after the interrupted HLT
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rather than to the HLT instruction)
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FF04h DWORD (undoc) I/O restart EDI / CR0
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FF08h DWORD (undoc) I/O restart ECX
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FF0Ch DWORD (undoc) I/O restart ESI
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FF10h DWORD (undoc) I/O restart EIP
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FF14h 16 BYTEs unused
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FF24h WORD (undoc) alternate DR6
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FF26h WORD (undoc) RSM control
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if bit 0 set on return, the low word of DR6 is loaded from FF26h
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instead of FFCCh
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FF28h DWORD (undoc) CR4
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FF2Ch DWORD unused
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FF30h 12 BYTEs (undoc) ES descriptor cache
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DWORD limit
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DWORD base address
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DWORD type
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FF3Ch 12 BYTEs (undoc) CS descriptor cache
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FF48h 12 BYTEs (undoc) SS descriptor cache
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FF54h 12 BYTEs (undoc) DS descriptor cache
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FF60h 12 BYTEs (undoc) FS descriptor cache
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FF6Ch 12 BYTEs (undoc) GS descriptor cache
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FF78h 12 BYTEs (undoc) LDT descriptor cache
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FF84h 12 BYTEs (undoc) GDT descriptor cache
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FF90h 12 BYTEs (undoc) IDT descriptor cache
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FF9Ch 12 BYTEs (undoc) TSS descriptor cache
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FFA8h WORD ES
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FFAAh WORD reserved
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FFACh WORD CS
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FFAEh WORD reserved
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FFB0h WORD SS
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FFB2h WORD reserved
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FFB4h WORD DS
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FFB6h WORD reserved
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FFB8h WORD FS
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FFBAh WORD reserved
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FFBCh WORD GS
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FFBEh WORD reserved
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FFC0h DWORD LDTR
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FFC4h DWORD TR
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FFC8h DWORD DR7
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FFCCh DWORD DR6
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FFD0h DWORD EAX
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FFD4h DWORD ECX
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FFD8h DWORD EDX
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FFDCh DWORD EBX
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FFE0h DWORD ESP
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FFE4h DWORD EBP
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FFE8h DWORD ESI
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FFECh DWORD EDI
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FFF0h DWORD EIP
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FFF4h DWORD EFLAGS
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FFF8h DWORD CR3
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FFFCh DWORD CR0
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SeeAlso: #S0003
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--------!---Admin----------------------------
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Highest Table Number = S0008
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--------!---FILELIST-------------------------
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Please redistribute all of the files comprising the interrupt list (listed at
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the beginning of the list and in INTERRUP.1ST) unmodified as a group, in a
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quartet of archives named INTER61A through INTER61D (preferably the original
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authenticated PKZIP archives), and the utility and hypertext conversion
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programs in two additional archives called INTER61E.ZIP and INTER61F.ZIP.
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Copyright (c) 1989-1999,2000 Ralf Brown
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--------!---CONTACT_INFO---------------------
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E-mail: ralf@pobox.com (currently forwards to ralf@telerama.lm.com)
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