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136 lines
6.9 KiB
136 lines
6.9 KiB
4 years ago
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iAPX 86 Interrupt Primer
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------------------------
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by Ralf Brown
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12/87
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Updated 6/88, 4/90, 9/92, 1/97
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What is an interrupt?
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---------------------
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An interrupt is a hardware signal that tells the CPU to temporarily
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stop what it is doing and go do something else. Without interrupts,
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the CPU would have to constantly check for external events; with
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interrupts, the CPU can work on something else and still respond to
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an event as soon as it occurs.
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CPUs typically have an instruction to disable interrupts for use
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when a section of code has to run without being disturbed by
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external events. Because of this, most CPUs also have a special
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interrupt called a Non-Maskable Interrupt (NMI), which is responded
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to even when all other interrupts are disabled. The NMI is used to
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signal calamities such as memory failure or imminent power loss.
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Why so many different interrupts?
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---------------------------------
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The 8086 family of processors has the ability to recognize 256
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different interrupts. They also have the ability to let a program
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invoke any of these interrupts with a special instruction, known as
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a software interrupt (as opposed to a hardware interrupt which is
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signalled from outside the processor). Software interrupts are
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treated just like hardware interrupts, except that they are never
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disabled and do not result in an acknowledgement to other chips in
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the computer. The software interrupt instruction on the 8086 family
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is called INT, and is given the number of the interrupt. Thus an
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INT 21h instruction invokes interrupt number 33 decimal.
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Other processors also have software interrupts, though they often
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use different names, such as the Motorola 68000 family TRAP
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instruction, the Intel 8080 RST (ReSTart) instruction, or many
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mainframes' SVC (SuperVisor Call).
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Since a program can invoke an interrupt by number rather than by its
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address (as it has to in calling subroutines), interrupts are a
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convenient way of providing services without having to recompile a
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program whenever the address of the code providing the service
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changes. This also allows a user program to enhance the services
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provided by directing the interrupt to itself. These enhanced
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services can then be made available to other programs.
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How does an interrupt work in real-address mode?
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------------------------------------------------
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The 8086 reserves the lowest 1024 bytes of memory for a table (IVT,
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Interrupt Vector Table) containing the addresses for each of the 256
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possible interrupts. When an interrupt occurs (hardware or
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software), the processor multiplies its number by 4 and looks at the
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resulting memory location to find the address of the piece of code
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which handles the interrupt. It then places the current address in
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the program and the processor flags on the stack, and jumps to the
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beginning of the interrupt handler.
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When the interrupt handler finishes, it invokes a special
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instruction to return from the interrupt. This instruction takes
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the previously saved flags and program address off of the stack and
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places them back in the appropriate registers in the CPU.
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The interrupt handler has to be careful to preserve any registers
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that it uses which are not used to communicate results to the
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program that invoked the interrupt. If the interrupt can be
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triggered by a hardware interrupt (only certain ones can on IBM
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PC's, XT's, and AT's), then the interrupt handler has to preserve
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ALL registers, since the interrupt could have happened anywhere.
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How does an interrupt work in protected mode?
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---------------------------------------------
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The 80286 and later processors can also operate in protected mode,
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in which case the interrupt handling is somewhat different. First,
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the interrupt table consists of eight-byte descriptors instead of
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four-byte addresses, and need not be located at physical address
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zero, nor contain the full 256 entries (the address and size of the
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Interrupt Descriptor Table (IDT) may be manipulated with the LIDT
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and SIDT instructions).
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Second, in protected mode, the descriptor for an interrupt number
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specifies HOW control is transferred to the interrupt handler.
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Three types of transfer are possible: Interrupt Gate, Trap Gate,
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and Task Gate. The first two types transfer control to a handler
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running in the same process as the active program, while a Task Gate
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performs a complete context switch in order to invoke a handler in
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a different process from the active program. Interrupt and Trap
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gates are identical except that an Interrupt Gate will clear IF
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and thus disable interrupts, while a Trap Gate leaves IF unchanged.
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How does an interrupt work in virtual-86 (V86) mode?
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----------------------------------------------------
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The 80386 and later processors provide a virtual-8086 mode which is
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a protected mode that appears to software to be the same as Real
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mode. Because it is a protected mode, however, interrupts and
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various other actions that potentially affect system integrity do
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not execute directly, but instead invoke a supervisor program running
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in standard protected mode. Thus, whenever a program running in
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V86 mode invokes an interrupt call, the CPU switches to protected
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mode and transfers control to the interrupt handler specified by
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the protected-mode IDT, rather than the real-mode IVT. The
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supervisor program may handle the interrupt call in any way it
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likes, but typically switches the CPU back into V86 mode and jumps
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to the address specified in the real-mode IVT (a process which is
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known as "reflecting" the interrupt).
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GLOSSARY
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--------
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API (Application Program[ming] Interface)
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An API is the set of function calls and services that a program
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makes available to other processes (applications). Each function or
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service has a set format which specifies the values to be supplied
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by the caller and the values which are returned. Because of this
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interface specification, the underlying organization of the function
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or service can be changed without affecting the applications which
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use it. For example, the DOS INT 21h file access functions remained
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unchanged between DOS 2.x and DOS 3.x, even though the internal data
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structures and code organization changed significantly.
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IDT (Interrupt Descriptor Table)
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IVT (Interrupt Vector Table)
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NMI (Non-Maskable Interrupt)
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Most external (hardware) interrupts can be disabled by the CLI
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(CLear Interrupt enable flag) instruction when the CPU is executing
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critical code that should not be interrupted, such as switching from
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one stack to another. However, there are some situations so dire
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that the CPU must act on them immediately no matter what else it is
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doing, even if it has disabled interrupts. The Non-Maskable
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Interrupt serves precisely this purpose, as it cannot be disabled
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(masked) by the CPU.
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